Modular digital image processing via an image processing chain with modifiable parameter controls

ABSTRACT

Aspects for allowing variably controlled alteration of image processing of digital image data in a digital image capture device include forming an image processing chain with two or more image processors to process digital image data, and providing one or more parametric controls within each of the two or more image processors. The aspects further include accessing chosen controls of the one or more parametric controls to modify the two or more image processors for alteration of the image processing.

RELATED APPLICATIONS

The present invention is related to co-pending U.S. patent application,Ser. No. 08/705,619, filed on Aug. 29, 1996, entitled MODULAR DIGITALIMAGE PROCESSING VIA AN IMAGE PROCESSING CHAIN, and assigned to theassignee of the present invention.

The present invention is also related to co-pending U.S. patentapplication, Ser. No. 08/705,588, filed on Sep. 29, 1996, entitledFLEXIBLE DIGITAL IMAGE PROCESSING VIA AN IMAGE PROCESSING CHAIN WITHMODULAR IMAGE PROCESSORS, and assigned to the assignee of the presentinvention.

FIELD OF THE INVENTION

The present invention relates to digital image data processing, and moreparticularly to modular digital image data processing with modifiableparameter control.

BACKGROUND OF THE INVENTION

Modern digital cameras typically include an imaging device which iscontrolled by a computer system. The computer system accesses raw imagedata captured by the imaging device and then processes and compressesthe data before storing the compressed data into an internal memory. Theconventional digital camera captures image data and then remainsunusable until the data is completely processed and stored into internalflash memory.

In processing image data, typical digital cameras operate with exclusiveand specific image processing. Thus, all the potential manipulations onimage data, such as linearization, sharpening, and compression, occur asa result of isolated preset programming and/or specifically designedhardware.

While some level of manipulation of image data is achieved with theprogramming or hardware, attempts to alter and improve the processingare hampered by the rigid structure of using a single file/specificcomponents. Furthermore, camera functionality remains tied to technologyavailable at the time of the design and is not readily replaced andupdated as technology improves. Accordingly, a need exists for a moreflexible, modular approach for processing digital image data thatprovides enhanced digital image output through an adaptable imageprocessing system.

SUMMARY OF THE INVENTION

Accordingly, the present invention meets these needs and provides amethod and system for allowing variably controlled alteration of imageprocessing of digital image data in a digital image capture device. In amethod aspect, the method includes forming an image processing chainwith two or more image processors to process digital image data, andproviding one or more parametric controls within each of the two or moreimage processors. The method further includes accessing chosen controlsof the one or more parametric controls to modify the two or more imageprocessors for alteration of the image processing.

In a system aspect, the system includes a digital image capture device,the digital image capture device capable of processing digital imagedata through two or more image processors, the two or more imageprocessors having one or more parametric controls, and a centralprocessing unit. The central processing is included within the digitalimage capture device and capable of linking the two or more imageprocessors to form an image processing chain. The central processingunit further facilitates access of chosen controls of the one or moreparametric controls for modification of the two or more image processorsand alteration of the image processing.

With the present invention, processing of digital image data occurs witha linked series of image processors. Each of the image processorsperforms some level of manipulation of the digital image data. Theseparation of digital image processing into a series of image processorsallows a more modular approach to processing digital image data.Further, the present invention uniquely allows modification of theseries through deletion of an image processor, insertion of a differentimage processor, or replacement of an existing image processor. Inaddition, aspects of an image processor, including parameter controlvalues, are alterable in accordance with a preferred embodiment to allowgreater adaptability to user-specific design preferences. Enhancementsand changes to the chain are therefore easily achieved, allowing greaterflexibility and more convenient upgrading of digital image processing.

These and other advantages of the aspects of the present invention willbe more fully understood in conjunction with the following detaileddescription and accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a digital camera that operates inaccordance with the present invention.

FIG. 2 is a block diagram of the preferred embodiment for the imagingdevice of FIG. 1.

FIG. 3 is a block diagram of the preferred embodiment for the computerof FIG. 1.

FIG. 4 is a memory map showing the preferred embodiment of the read onlymemory (ROM) of FIG. 3.

FIG. 5 is a block diagram showing preferred data paths for transmittingimage data between components of the FIG. 3 computer.

FIG. 6 illustrates an image processing chain of three image processors.

FIG. 7 illustrates a more specific example of the image processingchain.

FIG. 8 illustrates an image processing backplane in conjunction with theimage processing chain of FIG. 6.

DETAILED DESCRIPTION

The present invention relates to a flexible, modular approach toprocessing of digital image data. The following description is presentedto enable one of ordinary skill in the art to make and use the inventionand is provided in the context of a patent application and itsrequirements. Various modifications to the preferred embodiment and thegeneric principles and features described herein will be readilyapparent to those skilled in the art.

Although the following describes processing of digital image datacaptured through a digital camera device, it is meant as an illustrativeembodiment of the features of the present invention. The presentinvention is equally capable of utilization with other devices thatperform digital image data capture and processing, including, but notlimited to, computer systems, including those used to capture digitalimages accessible from Internet sites and image scanner equipment.Further, the data structures and commands discussed with reference to apreferred embodiment are suitably included as part of high level codeused directly by one or more applications that is readily achievedthrough the use of C, C++, or other similar programming language, andstored on a computer readable medium.

A digital camera architecture has been disclosed in co-pending U.S.patent application Ser. No. 08/666,241, entitled "A System And MethodFor Using A Unified Memory Architecture To Implement A Digital CameraDevice," filed on Jun. 20, 1996, and assigned to the Assignee of thepresent application. The Applicant hereby incorporates the co-pendingapplication by reference, and reproduces portions of that applicationherein with reference to FIGS. 1-5 for convenience.

Referring now to FIG. 1, a block diagram of a camera 110 is shownaccording to the present invention. Camera 110 preferably comprises animaging device 114, a system bus 116 and a computer 118. Imaging device114 is optically coupled to an object 112 and electrically coupled viasystem bus 116 to computer 118. Once a photographer has focused imagingdevice 114 on object 112 and, using a capture button or some othermeans, instructed camera 110 to capture an image of object 112, computer118 commands imaging device 114 via system bus 116 to capture raw imagedata representing object 112. The captured raw image data is transferredover system bus 116 to computer 118 which performs various imageprocessing functions on the image data before storing it in its internalmemory. System bus 116 also passes various status and control signalsbetween imaging device 114 and computer 118.

Referring now to FIG. 2, a block diagram of the preferred embodiment ofimaging device 114 is shown. Imaging device 114 preferably comprises alens 220 having an iris, a filter 222, an image sensor 224, a timinggenerator 226, an analog signal processor (ASP) 228, ananalog-to-digital (A/D) converter 230, an interface 232, and one or moremotors 234.

U.S. patent application Ser. No. 08/355,031, entitled "A System andMethod For Generating a Contrast Overlay as a Focus Assist for anImaging Device," filed on Dec. 13, 1994, is incorporated herein byreference and provides a detailed discussion of the preferred elementsof imaging device 114. Briefly, imaging device 114 captures an image ofobject 112 via reflected light impacting image sensor 224 along opticalpath 236. Image sensor 224 responsively generates a set of raw imagedata representing the captured image 112. The raw image data is thenrouted through ASP 228, A/D converter 230 and interface 232. Interface232 has outputs for controlling ASP 228, motors 234 and timing generator226. From interface 232, the raw image data passes over system bus 116to computer 118.

Referring now to FIG. 3, a block diagram of the preferred embodiment forcomputer 118 is shown. System bus 116 provides connection paths betweenimaging device 114, power manager 342, central processing unit (CPU)344, dynamic random-access memory (DRAM) 346, input/output interface(I/O) 348, read-only memory (ROM) 350, and buffers/connector 352.Removable memory 354 connects to system bus 116 via buffers/connector352. Alternately, camera 110 may be implemented without removable memory354 or buffers/connector 352.

Power manager 342 communicates via line 366 with power supply 356 andcoordinates power management operations for camera 110. CPU 344typically includes a conventional processor device for controlling theoperation of camera 110. In the preferred embodiment, CPU 344 is capableof concurrently running multiple software routines to control thevarious processes of camera 110 within a multi-threading environment.DRAM 346 is a contiguous block of dynamic memory which may beselectively allocated to various storage functions.

I/O 348 is an interface device allowing communications to and fromcomputer 118. For example, I/O 348 permits an external host computer(not shown) to connect to and communicate with computer 118. I/O 348also permits a camera 110 user to communicate with camera 110 via anexternal user interface and via an external display panel, referred toas a view finder.

ROM 350 typically comprises a conventional nonvolatile read-only memorywhich stores a set of computer-readable program instructions to controlthe operation of camera 110. ROM 350 is further discussed below inconjunction with FIG. 4. Removable memory 354 serves as an additionalimage data storage area and is preferably a non-volatile device, readilyremovable and replaceable by a camera 110 user via buffers/connector352. Thus, a user who possesses several removable memories 354 mayreplace a full removable memory 354 with an empty removable memory 354to effectively expand the picture-taking capacity of camera 110. In thepreferred embodiment of the present invention, removable memory 354 istypically implemented using a flash disk.

Power supply 356 supplies operating power to the various components ofcamera 110. In the preferred embodiment, power supply 356 providesoperating power to a main power bus 362 and also to a secondary powerbus 364. The main power bus 362 provides power to imaging device 114,I/O 348, ROM 350 and removable memory 354. The secondary power bus 364provides power to power manager 342, CPU 344 and DRAM 346.

Power supply 356 is connected to main batteries 358 and also to backupbatteries 360. In the preferred embodiment, a camera 110 user may alsoconnect power supply 356 to an external power source. During normaloperation of power supply 356, the main batteries 358 provide operatingpower to power supply 356 which then provides the operating power tocamera 110 via both main power bus 362 and secondary power bus 364.

During a power failure mode in which the main batteries 358 have failed(when their output voltage has fallen below a minimum operationalvoltage level) the backup batteries 360 provide operating power to powersupply 356 which then provides the operating power only to the secondarypower bus 364 of camera 110. Selected components of camera 110(including DRAM 346) are thus protected against a power failure in mainbatteries 358.

Power supply 356 preferably also includes a flywheel capacitor connectedto the power line coming from the main batteries 358. If the mainbatteries 358 suddenly fail, the flywheel capacitor temporarilymaintains the voltage from the main batteries 358 at a sufficient level,so that computer 118 can protect any image data currently beingprocessed by camera 110 before shutdown occurs.

Referring now to FIG. 4, a memory map showing the preferred embodimentof ROM 350 is shown. In the preferred embodiment, ROM 350 includescontrol application 400, toolbox 402, drivers 404, kernal 406 and systemconfiguration 408. Control application 400 comprises programinstructions for controlling and coordinating the various functions ofcamera 110. Toolbox 402 contains selected function modules includingmemory manager 410, RAM spooler 1 (412), RAM spooler 2 (414), removablememory spooler 1 (416), removable memory spooler 2 (418), imageprocessing and compression 420 and file system 422.

Referring now to FIG. 5, a block diagram showing preferred data pathsfor transmitting image data between selected computer 118 components isshown. In FIG. 5, frame buffer 536 receives and stores raw image datapreviously captured by image device 114. Frame buffer 536 then transferscontrol of the raw image data to RAM spooler 1 (412) via line 610.Alternatively, if RAM disk 532 is full, frame buffer 536 may transfercontrol of the raw image data directly to image processing/compression420 using line 612. If RAM spooler 1 (412) receives control of the rawimage data, it then stores the raw image data into RAM disk 532 usingline 614.

Removable memory spooler 1 (416) may then access the raw image data fromRAM disk 532 via line 616 and store it into removable memory 354 usingline 618. Alternatively, if removable memory 354 is full or is notinserted, RAM disk 532 may provide the raw image data directly to imageprocessing/compression 420 using line 620. If removable memory spooler 1(416) stores the raw image data into removable memory 354, then imageprocessing/compression 420 typically accesses the stored raw image datausing line 622.

LINKING IMAGE PROCESSORS FOR FORMING IMAGES

In the preferred embodiment, image processing and compression 420 occursvia an image processing chain (IPC). For purposes of this discussion,the IPC preferably refers to a software process that manipulates imagedata in a stage by stage fashion. As shown in FIG. 6, an IPC 500 issuitably composed of a sequence of image processors 502 with each imageprocessor 502 performing a particular type of image transformation. Theinput image data 504 is suitably received from a single image source andoutput as output image data 506 into a single image destination. Imageprocessors suitably refer to software modules that apply algorithms onimage data to obtain a special image processing result, specificexamples of which are described below with reference to FIG. 7.

FIG. 7 illustrates the IPC 500 with several examples of the imageprocessors 502 capable for utilization as the IPC 500. For each of theimage processors 502, an unambiguous image data format is specified forthe input and output data. When the input and output image data formatsare the same, the image processor 502 is considered non-transforming,examples of which are represented by the rounded boxes in FIG. 7.Conversely, image processors 502 that do not have the same input andoutput data formats are suitably considered transforming, e.g., therectangles of FIG. 7. Although the following description of FIG. 7 isgiven with a particular order and series of image processors for imageprocessing to occur in a sequential and serial manner, it should beappreciated that in the preferred embodiment, any number ofnon-transforming image processors may be chained between two separatetransforming image processors. Further, brief descriptions of the typeof image processing capable by each image processor 502 are included asexamples. However, the details of such processing are not included inthe present discussion and are considered to be well understood by thoseskilled in the art. Thus, image processing through the use of otherimage processors in the IPC 500 is within the spirit and scope of thepresent invention.

The image processors 502 suitably include a first image processor 502afor linearization of the input image data 504. By way of example,linearization refers to a straightforward conversion of the image datafrom an eight-bit non-linear space to sixteen-bit linear space. As amore specific example, input pixels stored as eight bit compressed Bayerpattern image data are converted through linearization image processor502a into sixteen bit extended Bayer pattern image data.

A next suitable image processor 502b is a bad pixel replacementprocessor. Bad pixel replacement suitably occurs through interpolationof the neighborhood pixels around the defective CCD pixels. Theprocessing by image processor 502b capably receives and outputs pixeldata in sixteen-bit linear space Bayer format.

As a next image processor 502, white balance processor 502c performswhite balance image processing. Pixel data received and output by thewhite balance image processor 502c are appropriately stored insixteen-bit linear space Bayer format.

A fourth image processor 502d preferably performs image color or colorfilter array data (CFA) reconstruction. By way of example, the CFAreconstruction image processor 502d suitably achieves an interpolationoperation to convert sixteen-bit Bayer CFA pattern CCD data into aforty-eight bit extended RGB image.

Following CFA reconstruction image processor 502d, color transformationimage processor 502e is included. An appropriate color transformationimage processor 502e employs a color correction matrix, such as toconvert from device-dependent camera color space to device-independentlinear CCIR709 color space. Preferably, the input and output pixel datais stored in forty-eight bit extended RGB format.

As a next image processor, YCC color space transformation imageprocessor 502f is included. The YCC color space conversion imageprocessor 502f suitably uses CCIR 601-2 specification to create aneight-bit YCrCb image from an RGB image. Input pixel data to imageprocessor 502f is suitably given in forty-eight bit extended RGB formatwith output pixel data in twenty-four bit YCrCb444 format.

Two additional image processors 502 in the IPC 500 include sharpeningimage processor 502g and JPEG compression image processor 502h.Sharpening image processor 502g suitably receives input pixel data intwenty-four bit YCrCb format and outputs pixel data in the same formatafter performing sharpening operations. Parameter control of thesharpening suitably occurs with a range of values for the sharpeningoperation.

The JPEG compression image processor 502h suitably performs JFIF baseline image compression. Input pixel data in twenty-four bit YCrCb444format is output from image processor 502h as compressed and subsampledYCC format, 48-bit YCrCb411 per 4-pixel data. Two forms of parametercontrols are achieved via image processor 502h to both control thedegree of compression, e.g., maximum to normal to lossless, and toidentify data as color or grayscale.

Coordination of the image processors 502 to form the IPC 500 ispreferably done via an image processing backplane (IPB). In a preferredembodiment, the image processing backplane provides processing supportin a broad manner to allow varying algorithms to be incorporated asimage processors 502. The features of the processing support by the IPBare described in more detail with reference to FIG. 8 and includeperforming image scan line buffer input/output (I/O), IPC constructionand connection, image processor parameter control setting, single passthrough image data, procedural interface to the image processors,circular data pipeline support, and ring-pixel handling, with minimalmemory requirements and overheads.

FIG. 8 illustrates schematically an IPB 520 in conjunction with an IPC500 including two image processors 502. Suitably, internal datastructures, e.g., IPBImageBuf 522 and IPBNode 524, are maintained by theIPB 520 for storing information related to the image processors 502during processing and are connected indirectly in terms of data flow, asindicated by the dashed arrows in FIG. 8. The information maintained bythe data structures 522 and 524 preferably includes locations of theinput and output line buffers, and internal state and functional routineentry pointers of each image processor 502. Thus, data structure 522capably contains pointers pointing to image scan line buffers 526 thatare used to store input and output image data in formats suitablydetermined during installation of an image processor 502. Moreparticularly, the image scan line buffers 526 preferably store one ormore image scan lines, i.e., the lines of data forming a data pipelinethat consists of the minimum number of lines required by an imageprocessor 502.

For image processors 502, processing suitably occurs with a datapipeline that contains a single image scan line, i.e., an image pixelline in the fast scan direction from left to right. However, some imageprocessors 502, such as compression image processors (e.g., 502h, FIG.7), utilize more than one scan line during processing to takeneighboring effects into account. When more than one scan line is neededby an image processor 502, a data pipeline is suitably defined forconvenience at the input end of the image processor 502. For purposes ofthis discussion, a data pipeline refers to a minimum collection of imagescan lines required by an image processor 502. Generally, a datapipeline includes an image scan line currently being processed, and somenumber of image scan lines prior to (`lookback`) and/or after(`lookahead`) the current image scan line. Suitably, access to the datapipeline occurs via a circular array of buffer pointers, so that aftereach processing iteration of the image processor 502, the pointers inthe array are circularly rotated, as is well understood by those skilledin the art. In contrast to prior devices that typically require largeamounts of memory to perform image data manipulations, the image scanline buffers provide sufficient memory to perform processing one scanline at a time, thus reducing the overall memory requirements withoutreducing processing capabilities.

Preferably, the data pipeline required by an image processor 502 isindicated during the installation of the image processor 502 in the IPC500. Installation of an image processor 502 suitably occurs when thecamera first starts up with an IPC 500 constructed from all of thedefault image processors 502 stored in the system ROM. Suitablefunctions to coordinate the construction and deconstruction of the IPC500 include four functions, an initialization function, e.g., IPCInit,an installation function, e.g., IPCInstallImageProcessor, a connectionfunction, e.g., IPCConnect, and a destruction function, e.g.,IPCDestroy.

The IPC initialization function is called to create a new IPC 500. Asuitable default IPC 500 converts raw CCD capture data into a JPEGcompressed image. Preferably, the IPC initialization function returns areference to a new image processing chain, identifies types of imageprocessors included in the chain, and specifies a maximum expected widthin pixels to be sent through the IPC, where the maximum width includesring-pixels, which refer to supplementary image data at each side of theimage required by an image processor to perform a particular algorithm.

The IPC installation function is called by an image processingapplication to the IPB 520 to install the image processor 502 into theIPC 500. Preferably, the installation function specifies an IPCreference number, as identified in the initialization function, andprovides pointers to the seven functional routine entries, as discussedhereinbelow, of the image processor being installed.

The IPC connection function specifies an IPC reference number, andsignals to the IPB 520 that all image processors 502 have been installedand that the IPC 500 contains all the required image processors 502 toperform image processing. The IPC destruction function specifies an IPCreference number and is called to destroy an IPC 500. Although a defaultcamera IPC 500 is unlikely to be destroyed, other IPCs added to a camerafor other purposes, by functions in accordance with a preferredembodiment and discussed in more detail hereinbelow, are suitablydestroyed with this function.

MODULARITY OF IMAGE PROCESSORS THROUGH FLEXIBLE UPDATING OF AN IPC

Alterations to an existing IPC 500 readily occur in a preferredembodiment through an update function, e.g., IPBUpdateDefaultIPC, thatspecifies the IPC reference number for the IPC 500 beingupdated/modified. Updating of an IPC 500 includes insertion of an imageprocessor 502 to the IPC 500, deletion of an image processor 502 fromthe IPC 500, or replacement of an image processor 502 with an alternateimage processor 502. Preferably, the default IPC 500 is updated via animage processor module on a storage device, e.g., removable memory, RAMdisk, or internal memory. The image processor module suitably containsone or more plug-in image processors that each have one additionalfunction, e.g., IPMPlugInProc, that defines the updating strategy, thesignature of the target image processor to be updated, and pointers ofthe seven basic functions of an image processor, as describedhereinbelow. Lack of identification of valid target image processors inan IPC or lack of match between the format of the output of one imageprocessor and input of a next image processor chained togetherpreferably results in cancellation of the updating attempt andrestoration of the default IPC 500.

Defining an image processor 502, for use in a default IPC 500 or as anupdating image processor, suitably occurs through seven functionalroutines or procedures, as indicated by block 528 in FIG. 8. Adefinition function, e.g., IPDefineProc, allows an image processor 502to specify its characteristics. It is appropriately called by the IPB520 when the image processor 502 is installed into the IPC 500 toidentify the characteristics of the image processor 502. By way ofexample, for an image processor 502 that performs color correction via a3×3 matrix, input and output formats of 48 bit extended RGB are capablyidentified by the definition function. Further characteristicsidentified include the configuration of the data pipeline associatedwith the image processor 502, the number of ring-pixels, and the numberof parameter controls.

An initialization function, e.g., IPInitProc, appropriately allows animage processor 502 to allocate any internal storage it might need whenprocessing an image. It is suitably called by the IPB 520 only once whenthe image processor 502 is installed into the IPC 500. Subsequent callsto the other five functions described below then pass the internalstorage space allocated by the IPInitProc as an argument. Furtheridentified by the initialization function is the maximum widthspecification of an image scan line in pixels that is expected at theinput, including ring-pixels at both the left and right sides. In theexample of defining the color correction image processor, theinitialization function capably identifies a memory location storing apointer to needed 3×3 matrix constant value internal variables, and themaximum width.

Two functions, a control function, e.g., IPControlProc, and a statusfunction, e.g., IPStatusProc, deal with parameter controls of an imageprocessor 502. Preferably, parameter controls for an image processor 502each have a unique 4-character tag that is registered to avoid conflict.Parameter control values include two types, a range type and anenumerated list type. Range types of parameter control values areappropriately confined between the minimum and maximum settings for therange. Enumerated list parameter control values assign differentenumerated numbers to different settings with a 32-character nullterminated string used to provide an ASCII name for each enumerated listnumber. Examples of parameter controls include sharpening values (rangetype), color specification control values (range type), and compressioncontrol values (enumerated list type).

The control function, IPControlProc, is called by the IPB 520 to controlthe processing parameters one parameter control at a time and onlybefore a reset function, e.g., IPReset, call for every image to beprocessed. The status function, IPStatusProc, allows an image processor502 called by the IPB 520 to determine any parameter kind, values types,factory default parameter setting, and current parameter setting of animage processor 502. No-operation routines are provided when the imageprocessor does not support any parameter settings, such as in theexample of the color correction image processor.

The reset function, IPResetProc, suitably allows IPB 520 to signal animage processor 502 to reset any internal variables used by the imageprocessor 502 before every image is processed. With the color correctionimage processor example, no operation routines are provided, since nolocal variables need to be reset. A process function, e.g.,IPProcessProc, suitably allows an image processor 502 to process imagedata one scan line at a time. It is suitably called whenever a datapipeline for the image processor 502 fills up. Thus, the operations forperforming the 3×3 matrix manipulation in the color correction imageprocessor example, are specified with the process function. Adestruction function, e.g., IPDestroyProc, suitably allows an imageprocessor to deallocate any internal storage allocated atinitialization. It is appropriately called when the IPC 500 containingthe image processor 502 is being removed. In response to this call, theimage processor 502 preferably deallocates internal storage allocated inthe initialization function call.

Entry points to these seven functional routines for an image processor502, stored in an external data structure, e.g., Functions, as well asthe characteristics of the image processor 502, are suitably stored inan internal data structure, e.g., ImageProc, by the IPB 520. Once theimage processors 502 are defined through the seven functional routinesand connected in an IPC 500, the IPB 520 suitably facilitates imageprocessing operations by managing image buffer I/O, and activation ofeach image processor 502 as soon as enough input data has beencollected. The information for the image data processed is suitablystored in a data structure, e.g., ImageInfo, including raw image sizecaptured by a camera CCD, final processed output image size, bad pixellocations, etc.

MODIFIABLE PARAMETER CONTROL OF IMAGE PROCESSOR IN AN IPC

In a preferred embodiment, the IPB 520 further provides routines toallow exchanges of parameter control settings by an external mechanism,such as a control application 400 (FIG. 4). These functions includeparameter control capability and value determination functions, e.g.,IPBGetParameterCapability, IPBGetDefaultParameter, and IPBGetParameter.Also included are functions for setting or restoring parameter controlvalues, e.g., IPBSetDefaultParameter, IPBSetParameter, andIPBRestoreParameter. Preferably, for the parameter control valuedetermination functions, an IPC 500 and the number of parametersrequested are identified, as well as identification of a pointer to anarray of parameter tags, a pointer to a memory location used to store apointer for the parameter settings returned, and a pointer to a memorylocation where the number of bytes of parameter control values arestored. Similarly, for the capability determination function, an IPC isspecified, the number of parameters requested is specified, a pointer toan array of parameter tags is specified, a pointer to a memory locationused to store a pointer for the parameter capability informationreturned is specified, and a pointer to a memory location where thenumber of bytes of parameter capability information is stored isspecified. Thus, access to the parameter controls managed by an IPC 500are available, as well as current values, device dependent factorydefault values, and user-specified default values.

For the parameter control value setting functions, preferably identifiedby the functions are an IPC, a number of parameter control values to beset, and a pointer to a list of parameter tags and either a currentvalue or a user default value that are to be set by the function. Inaddition, the set parameter function appropriately allows all parametersnot listed in the specified parameter value list to be reset to theiruser default value when a Boolean variable is set. The restorationfunction similarly identifies an IPC and a number of parameters to berequested, provides a pointer to an array of parameter tags, and selectsthe type of parameter defaults, i.e., user-specified or device dependentfactory, being reset through a Boolean variable. These functionstherefore provide convenient accessibility to allow alteration ofparameter control values in an IPC 500. Greater flexibility foradjusting an image processor 502 within an IPC 500 is advantageouslyprovided.

Although the present invention has been described in accordance with theembodiments shown, one of ordinary skill in the art will recognize thatthere could be variations to the embodiment and those variations wouldbe within the spirit and scope of the present invention. Accordingly,many modifications may be made by one of ordinary skill withoutdeparting from the spirit and scope of the present invention, the scopeof which is defined by the following claims.

What is claimed is:
 1. A method for allowing variably controlled alteration of image processing of digital image data in a digital image capture device, the method comprising:forming an image processing chain with two or more image processors, the two or more image processors being stored in memory, wherein said processors are software modules and each performing a particular type of image transformation, to process digital image data; providing one or more parametric controls that are uniquely identified and within each of the two or more image processors; and accessing chosen controls of the one or more parametric controls within each of the two or more image processors to modify the two or more image processors for alteration of the image processing.
 2. The method of claim 1 wherein the step of accessing further comprises altering a default value of the one or more parametric controls.
 3. The method of claim 2 wherein the step of altering further comprises setting the default value to a desired value.
 4. The method of claim 2 wherein the step of altering further comprises resetting the default value to a device dependent factory value.
 5. The method of claim 1 wherein the step of accessing further comprises determining current values of the one or more parametric controls.
 6. The method of claim 1 wherein the step of accessing further comprises determining default values of the one or more parametric controls.
 7. The method of claim 1 wherein the step of accessing further comprises determining parametric control capabilities of the one or more parametric controls.
 8. The method of claim 7 wherein the step of determining parametric control capabilities further comprises providing values, value types, and device dependent factory default values.
 9. The method of claim 1 wherein the two or more image processors further comprise a sharpening image processor and a compression image processor.
 10. The method of claim 9 wherein the sharpening image processor provides a sharpening parametric control.
 11. The method of claim 10 wherein the sharpening parametric control comprises a range type of control.
 12. The method of claim 9 wherein the compression image processor provides a compression parametric control and a color specification control.
 13. The method of claim 12 wherein the compression parametric control comprises an enumerated list type of control.
 14. The method of claim 12 wherein the color specification parametric control comprises a range type of control.
 15. A system for allowing variably controlled alteration of image processing of digital image data, the system comprising:a digital image capture device, the digital image capture device capable of processing digital image data through two or more image processors, the two or more image processors being stored in memory, wherein said processors are software modules and each performing a particular type of image transformation and having one or more parametric controls that are uniquely identified; and a central processing unit within the digital image capture device and capable of linking the two or more image processors to form an image processing chain, wherein the central processing unit facilitates access of chosen controls of the one or more parametric controls within each of the two or more image processors for modification of the two or more image processors and alteration of the image processing.
 16. The system of claim 15 wherein the two or more image processors further comprise a sharpening image processor and a compression image processor.
 17. The system of claim 15 wherein the central processing unit facilitates altering a default value of the one or more parametric controls.
 18. The system of claim 15 wherein the central processing unit facilitates setting the default value to a desired value.
 19. The system of claim 15 wherein the central processing unit facilitates resetting the default value to a device dependent factory default value.
 20. The system of claim 15 wherein the central processing unit facilitates determining current values of the one or more parametric controls.
 21. The system of claim 15 wherein the central processing unit facilitates determining default values of the one or more parametric controls.
 22. The system of claim 15 wherein the central processing unit facilitates determining parametric control capabilities of the one or more parametric controls, including values, value types, and device dependent factory default values.
 23. A computer readable medium containing program instructions for:forming an image processing chain with two or more image processors, the two or more image processors stored in memory, wherein said processors are software modules and each performing a particular type of image transformation, to process digital image data; providing one or more parametric controls that are uniquely identified and within each of the two or more image processors; and accessing chosen controls of the one or more parametric controls within each of the two or more image processors to modify the two or more image processors for alteration of the image processing. 